A Numerical Simulation of Hot-carrier Induced Device Degradation

For radical designs the hot-carrier reliability is an important issue. This creates the need for the numerical simulation of hot-carrier induced degradation. From a design point of view, the goal of the degradation simulation will be the hot-carrier aging simulation for the prediction of device lifetime. This simulation requires a complicated set of physical models, which includes the hot-carrier transport in silicon, emission process, carrier behavior in the oxide, carrier trapping, and charged interface state generation. An advanced simulation technique is also needed to obtain a self-consistent solution of the degradation under stress. Recently, several approaches are proposed [ 1 ] [ 3 ]. This paper describes a numerical simulation of hot-carrier induced degradation under dc stress. The physical model used here and simulation results are discussed with emphasis on the degradation behavior of the buried p-MOSFET's.